1. Field of the Invention
The present invention relates to an IC testing apparatus (commonly called IC tester) for testing a semiconductor integrated circuit (hereinafter referred to as IC), and more particularly, to a voltage applied type current measuring circuit utilized in testing a logic IC formed by, for example, a CMOS or CMOSs (Complementary Metal Oxide Semiconductor or Semiconductors) to determine whether a leakage current flows or not through input terminal pins of the logic IC (hereinafter referred to as CMOS.IC). Herein, the voltage applied type current measuring circuit means a circuit for applying a voltage to an IC under test and measuring a current flow through the IC.
2. Description of the Related Art
In an IC tester, a function test for applying a varying voltage to an IC under test (commonly called DUT) and measuring in what manner the output of the IC under test is varied can be performed at high speed for each input terminal pin of the IC under test.
A feature of the CMOS.IC which is one of various types of ICs is such that its input current is small or zero, but a circuit for measuring a minute or micro current is needed to test such CMOS.IC. However, such micro current measuring circuit is usually slow in response, and hence it is customary in the prior art that the measurement of current through a CMOS.IC is conducted separately of the function test thereof. FIG. 3 shows an example of an associated circuit part of a conventional IC tester having a voltage applied type current measuring circuit for measuring a minute or micro current through an IC under test.
There are provided, for each of pins of an IC under test (DUT) 11, a plurality of input/output blocks 12-1, 12-2, . . . , 12-n (n being an integer equal to the number of the pins of the IC under test and equal to or greater than one). Each input/output block (I/O block) comprises a driver 13 for applying a predetermined voltage to corresponding one of the pins of the IC under test 11, a comparator 16 for comparing an output voltage from the IC under test 11 with a reference voltage, and a voltage applied type current measuring circuit 17.
The output terminal of the driver 13 is connected to an input/output terminal 15 of that I/O block via a first switch 14, and the connection point (junction) of the output terminal of the driver 13 and the first switch 14 is connected to an input terminal of the comparator 16.
The voltage applied type current measuring circuit 17 comprises a digital-to-analog converter (D/A converter) 18, a buffer circuit 19 having its non-inverting input terminal connected to the output terminal of the D/A converter 18, a differential amplifier 23 having its inverting input terminal connected to the output terminal of the buffer circuit 19 and its non-inverting terminal connected to the output terminal of the D/A converter 18, and a current detecting resistance element 21 the input side of which is connected to the output terminal of the buffer circuit 19 and the output side of which is connected to the inverting input terminal of the buffer circuit 19 and one end of a second switch 22. Accordingly, the output terminal of the buffer circuit 19 is connected to the input/output terminal 15 of that I/O block via the current detecting resistance element 21 and the second switch 22 in series.
The output terminal of the differential amplifier 23 in each I/O block 12-i (i=1, 2, . . . , n) is connected to an analog-to-digital converter (AD converter) 25 via a switch 24-i (i=1, 2, . . . , n) provided in each of the I/O blocks. Further, an operating power supply 26 is connected to a power supply terminal pin of the IC under test 11.
In case of measuring a current flow through an IC under test under a predetermined voltage applied thereto, namely, in case of the voltage applied type current measurement, each of the input/output terminals of the I/O blocks 12-1 to 12-n is connected to corresponding one of the pins of the IC under test 11, a digital value set in correspondence to a testing voltage is inputted into the D/A converter 18 under the condition that the first switch 14 and the second switch 22 in each I/O block are turned off and on respectively, and then a testing voltage outputted from the D/A converter 18 is applied to each of the pins of the IC under test 11.
By this procedure, a voltage developed across the current detecting resistance element 21 in correspondence to a current flow through each pin of the IC under test 11 can be detected by the differential amplifier 23 constructed as stated below, and therefore, by sequentially turning on the switches 24-1 to 24-n one after another, a voltage corresponding to an input current flow into each I/O block which has been turned on, that is, to an input current flow into each pin of the IC under test 11 connected to that I/O block which has been turned on can be obtained from the A/D converter 25 as digital data.
The differential amplifier 23 actually has such a circuit construction, as shown in FIG. 4, that the inverting input terminal 27 thereof is connected to a non-inverting input terminal of a buffer 28, an output terminal of the buffer 28 is connected to an inverting input terminal thereof as well as to an inverting input terminal of a differential amplifier 31 via a first resistance element 29 (R1), a second resistance element 35 (R2) is connected between an inverting input terminal and an output terminal of the differential amplifier 31, the non-inverting input terminal 32 of the differential amplifier 23 is connected to a non-inverting input terminal of the differential amplifier 31 via a third resistance element 33 (R3), this non-inverting input terminal of the differential amplifier 31 is connected to the ground via a fourth resistance element 34 (R4), and an output element of the differential amplifier 31 is connected to the output terminal 36 of the differential amplifier 23. Accordingly, to the output terminal 36 of the differential amplifier 23 is outputted a difference voltage V.sub.C between the voltage V.sub.A at the inverting input terminal 27 and the voltage V.sub.B at the non-inverting input terminal 32, and a voltage corresponding to an input current flow into each pin of the IC under test 11 can be obtained from the A/D converter 25 as digital data.
The differential amplifier 23 must be designed by taking into consideration a common-mode rejection ratio (CMRR), that is, a characteristic of rate or ratio where signals inputted into the two input terminals 27 and 32 in phase with each other are rejected. If this common-mode rejection ratio is inappropriate, it is difficult to measure an input current with high accuracy. The common-mode rejection ratio is affected by errors in the resistance values of the resistance elements 29, 33, 34 and 35.
Letting the resistance values of the resistance elements 29, 35, 33 and 34 be represented by R1, R2, R3 and R4, respectively, and assuming that the resistance value of each of the resistance elements has an error .alpha., the relationship between voltage V.sub.A at the inverting input terminal 27, voltage V.sub.B at the non-inverting input terminal 32, and voltage V.sub.C at the output terminal 36 can be expressed by the following equation. ##EQU1##
Therefore, putting R1=R(1.+-..alpha.), R2=R(1.-+..alpha.), R3=R(1.-+..alpha.), R4=R(1.+-..alpha.), V.sub.A =V.sub.B, then V.sub.C =4.alpha.. For example, assuming that V.sub.B =5 V and .alpha.=0.1%, the error is 50.times.0.1%.times.4=20 mV at the maximum.
Since such a large error occurs, the minute current measurement requires to use the resistance elements 29, 33, 34 and 35 having extremely high-precision resistance values, respectively, which are very expensive resistance elements. In addition, it is necessary to correct errors in the operational amplifiers (buffers) and the A/D converter.